Data writing method for non-volatile memory, and controller and storage system using the same

ABSTRACT

A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation-in-part application of and claims the priority benefit of Patent Application No. 12/764,583, filed on Apr. 21, 2010, which claims the priority benefit of Taiwan application serial no. 99104816, filed on Feb. 12, 2010. This application also claims the priority benefit of Taiwan application serial no. 99141041, filed on Nov. 26, 2010. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Technology Field

The present invention relates to a data writing method for a non-volatile memory, and a re-writable non-volatile memory controller and a re-writable non-volatile memory storage system using the same.

2. Description of Related Art

Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media has increased drastically. Rewritable non-volatile memory is one of the most adaptable memories for such battery-powered portable products due to its characteristics such as data non-volatility, low power consumption, small volume, and non-mechanical structure. A flash drive is a storage apparatus adopting rewritable non-volatile memory as storage medium. Rewritable non-volatile memory has been broadly used for storing important personal data thanks to its small volume and large capacity. Therefore, the rewritable non-volatile memory industry has become a very important part of the electronic industry in recent years.

A memory die of a rewritable non-volatile memory storage apparatus has a plurality of physical blocks, and each physical block has a plurality of physical pages, wherein data must be written into a physical block according to the sequence of the physical pages in the physical block. In general, the procedure of writing data into a physical page may be divided into a data transfer portion and a data program portion. To be specific, when data is about to be stored into the physical page of the memory die, the control circuit of the rewritable non-volatile memory storage apparatus first transmits the data to the buffer of the memory die. Then, the memory die programs the data from the buffer into the physical page. During the control circuit of the rewritable non-volatile memory storage apparatus transmits the data to the buffer of the memory die, the memory die is at a transmission status. And, during the data is programmed into the physical page, the memory die is at a busy status.

In order to increase the writing speed of a rewritable non-volatile memory storage apparatus, a plurality of memory dies is disposed in the rewritable non-volatile memory storage apparatus and data is written in a interleave manner or a parallel manner. For example, taking a rewritable non-volatile memory storage apparatus having a first memory die and a second memory die, which coupled to a control circuit via one data input/output bus, as an example, when a host system is about to store a plurality of page data (i.e., data having the length that is larger than the capacity of one physical page) into the rewritable non-volatile memory storage apparatus, the control circuit may transmit one page data to the first memory die. After that, during the first memory die is at the busy status, the control circuit may transmit another page data to the second memory die. Then, during the second memory die is at the busy status, the control circuit may transmit another page data to the first memory die. Accordingly, the first and second memory dies are alternately received data from the control circuit and program the received data, thereby shortening the time for writing data.

In particular, when the memory die is at the transmission status or the busy status, the memory die needs power to transmitting data or programming data. However, in view of a flash drive operated with the power supplied by a data transmission interface of a host system, when several memory dies are enabled at the same time (i.e., several memory dies are at the transmission status or the busy status at the same time), the power supplied by the data transmission interface may be not enough, such that the stability of the rewritable non-volatile memory storage apparatus is reduced.

Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.

SUMMARY

The present invention relates to a data writing method for a rewritable non-volatile memory, which is capable of preventing the stability of the rewritable non-volatile memory storage apparatus from reducing due to the insufficient power supplied by a data transmission interface.

The present invention relates to a rewritable non-volatile memory controller executing a data writing method capable of preventing the stability of the rewritable non-volatile memory storage apparatus from reducing due to the insufficient power supplied by a data transmission interface.

The present invention relates to a rewritable non-volatile memory storage system executing a data writing method capable of preventing the stability of the rewritable non-volatile memory storage apparatus from reducing due to the insufficient power supplied by a data transmission interface.

According to an exemplary embodiment of the present invention, a data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided, wherein a host interface of the rewritable non-volatile memory storage apparatus is adapted for coupling to a data transmission interface of the host system. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard after the data transmission interface couples to the host interface. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a first power saving mode or a second power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Herein, the number of the memory dies that are enabled at the same time is not larger than a first amount and the memory dies operate with a first operation frequency in the general mode. In the first power saving mode, the number of the memory dies that are enabled at the same time is not larger than a second amount, wherein the second amount is smaller than the first amount. In the second power saving mode, the memory dies operate with a second operation frequency, wherein the second operation frequency is smaller than the first operation frequency.

According to an exemplary embodiment of the present invention, a rewritable non-volatile memory controller including a host interface, a rewritable non-volatile memory interface and a memory management circuit is provided. The host interface is configured for coupling to a host system. The rewritable non-volatile memory interface is configured for coupling to the above-mentioned memory dies. The memory management circuit couples to the host interface and the rewritable non-volatile memory interface, wherein the memory management circuit is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information. The memory management circuit uses a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a first amount in the general mode. The memory management circuit uses a first power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode and the second amount is smaller than the first amount.

A rewritable non-volatile memory storage system including a connector, a memory module having a plurality of memory dies and a rewritable non-volatile memory controller coupled to the memory module. Herein, the rewritable non-volatile memory controller is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information. The rewritable non-volatile memory controller uses a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a first amount in the general mode. The rewritable non-volatile memory controller uses a first power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode and the second amount is smaller than the first amount.

According to an exemplary embodiment of the present invention, a rewritable non-volatile memory controller for writing data from a host system into a plurality of memory dies is provided. The rewritable non-volatile memory controller includes a host interface, a rewritable non-volatile memory interface, power management circuit and a memory management circuit. The memory interface is configured to couple to a data transmission interface of the host system and the rewritable non-volatile memory interface is configured for coupling to the memory dies. The power management circuit has a phase locked loop (PLL). The memory management circuit is coupled to the rewritable non-volatile memory interface and the power management circuit. The power management circuit is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information; When the data transmission interface of the host system complies with the first interface standard, the PLL generates a first operation frequency and provides the first operation frequency for the memory management circuit and the memory dies and the memory management circuit writes the data into the memory dies with the first operation frequency. When the data transmission interface of the host system complies with the second interface standard, the PLL generates a second operation frequency and provides the second operation frequency for the memory management circuit and the memory dies and the memory management circuit writes the data into the memory dies with the second operation frequency.

According to an exemplary embodiment of the present invention, a non-volatile memory storage system including a connector, a memory module and a rewritable non-volatile memory controller is provided. The connector is configured for coupling to a host system, the memory module has a plurality of memory dies and the rewritable non-volatile memory controller couples to the memory module. The rewritable non-volatile memory controller is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information. When the data transmission interface of the host system complies with the first interface standard, the rewritable non-volatile memory controller generates a first operation frequency, provides the first operation frequency for the memory dies and writes the data into the memory dies with the first operation frequency. When the data transmission interface of the host system complies with the second interface standard, the rewritable non-volatile memory controller generates a second operation frequency, provides the second operation frequency for the memory dies and writes the data into the memory dies with the second operation frequency.

Based on the above, in the exemplary embodiment of the invention, the data writing method is capable of preventing the stability of the rewritable non-volatile memory storage apparatus from reducing due to the insufficient power during several memory dies are enabled for writing data.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below.

It should be understood, however, that this Summary may not contain all of the aspects and embodiments of the present invention, is not meant to be limiting or restrictive in any manner, and that the invention as disclosed herein is and will be understood by those of ordinary skill in the art to encompass obvious improvements and modifications thereto.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic flowchart of writing data according to an exemplary embodiment of the present invention.

FIG. 2A is a schematic block diagram of a host system using a rewritable non-volatile memory storage apparatus according to a first exemplary embodiment of the present invention.

FIG. 2B is a diagram illustrating a computer, an input/output (I/O) device, and a rewritable non-volatile memory storage apparatus according to an exemplary embodiment of the present invention.

FIG. 2C is a diagram of a host system and a rewritable non-volatile memory storage apparatus according to another exemplary embodiment of the present invention.

FIG. 3 is a schematic block diagram of the rewritable non-volatile memory storage apparatus in FIG. 2A.

FIG. 4 is a schematic block diagram of a rewritable non-volatile memory controller according to the first exemplary embodiment of the present invention.

FIG. 5 is a flowchart of recording the memory die that is at the transmission status according to the first exemplary embodiment of the present invention.

FIG. 6 is a flowchart of recording the memory die that is at the busy status according to the first exemplary embodiment of the present invention.

FIG. 7 is a flowchart of writing data in a first power saving mode according to the first exemplary embodiment of the present invention.

FIG. 8 is a flowchart of writing data according to the second exemplary embodiment of the present invention.

FIG. 9 is a schematic block diagram of a rewritable non-volatile memory controller according to a third exemplary embodiment of the present invention.

FIG. 10 is a flowchart of writing data according to the third exemplary embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Embodiments of the present invention may comprise any one or more of the novel features described herein, including in the Detailed Description, and/or shown in the drawings. As used herein, “at least one”, “one or more”, and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least on of A,B and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B, or C” and “A, B, and/or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.

It is to be noted that the term “a” or “an” entity refers to one or more of that entity. As such, the terms “a” (or “an”), “one or more” and “at least one” can be used interchangeably herein.

In order to prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to the insufficient power supplied by a data transmission interface, the present invention provides a method capable of using different data writing modes based on different data transmission interfaces. As shown in FIG. 1, in the present method, first, whether the data transmission interface of the host system complies with a first interface standard or a second interface standard is determined (S101). When the data transmission interface of the host system complies with the first interface standard, data is written into the memory dies by using a general mode (S103), wherein the number of memory dies that are enabled at the same time among the memory dies is not larger than a first amount in the general mode and the memory dies operate with a first operation frequency. When the data transmission interface of the host system complies with the second interface standard, data is written into the memory dies by using a first power saving mode or a second power saving mode (S105), wherein the number of memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode and the second amount is smaller than the first amount. And, in the second power saving mode, the memory dies operate with a second operation frequency, wherein the second operation frequency is smaller than the first operation frequency. In order to understand the present invention, several exemplary embodiments are described below to illustrate the present invention in detail.

First Exemplary Embodiment

A rewritable non-volatile memory storage apparatus (i.e., a rewritable non-volatile memory storage system), typically, includes a memory module and a controller (i.e., a control circuit). The rewritable non-volatile memory storage apparatus is usually used together with a host system so that the host system can write data into or read data from the rewritable non-volatile memory storage apparatus. In addition, a rewritable non-volatile memory storage apparatus also includes an embedded rewritable non-volatile memory and software that can be executed by a host system and substantially served as a controller of the embedded rewritable non-volatile memory.

FIG. 2A is a schematic block diagram of a host system using a rewritable non-volatile memory storage apparatus according to a first exemplary embodiment of the present invention.

Referring to FIG. 2A, a host system 1000 includes a computer 1100 and an input/output (I/O) device 1106. The computer 1100 includes a microprocessor 1102, a random access memory (RAM) 1104, a system bus 1108 and a data transmission interface 1110. The I/O device 1106 includes a mouse 1202, a keyboard 1204, a display 1206, and a printer 1208 as shown in FIG. 2B. It should be understood that the devices illustrated in FIG. 1B are not intended to limit the scope of the I/O device 1106, and the I/O device 1106 may further include other devices.

In the exemplary embodiment of the present invention, the rewritable non-volatile memory storage apparatus 100 is coupled to the devices of the host system 1000 through the data transmission interface 1110. By using the microprocessor 1102, the random access memory (RAM) 1104 and the Input/Output (I/O) device 1106, the data can be write into the rewritable non-volatile memory storage apparatus 100 or can be read from the rewritable non-volatile memory storage apparatus 100. For example, the rewritable non-volatile memory storage apparatus 100 may be a flash drive 1212, a memory card 1214, or a solid state drive (SSD) 1216, as shown in FIG. 2B.

Generally, the host system 1000 substantially could be any system capable of storing data. Even though the host system 1000 is described as a computer system in the present exemplary embodiment, in another exemplary embodiment of the present invention, the host system 1000 may also be a digital camera, a video camera, a communication device, an audio player, or a video player, and etc. For example, if the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage apparatus is then a SD card 1312, a MMC card 1314, a memory stick 1316, a CF card 1318 or an embedded storage device 1320 (as shown in FIG. 2C). The embedded storage device 1320 includes an embedded MMC (eMMC). It should be noted that the eMMC is directly coupled to the substrate of the host system.

FIG. 3 is a schematic block diagram of the rewritable non-volatile memory storage apparatus in FIG. 2A.

Referring to FIG. 3, the rewritable non-volatile memory storage apparatus 100 includes a connector 102, a rewritable non-volatile memory controller 104, and a memory module 106.

The connector 102 is coupled to the rewritable non-volatile memory controller 104 and configured for coupling to the host system 1000. In the present exemplary embodiment, the connector 102 is a Universal Serial Bus (USB) connector and complies with the USB 3.0 standard. Nevertheless, it should be understood that the present invention is not limited thereto, and the connector 102 may be other suitable connector.

The rewritable non-volatile memory controller 104 executes a plurality of logic gates or control instructions implemented in a hardware form or a firmware form and performs various data operations such as data writing, reading, and erasing in the memory module 106 according to commands from the host system 1000.

FIG. 4 is a schematic block diagram of a rewritable non-volatile memory controller according to the first exemplary embodiment of the present invention.

Referring FIG. 4, the rewritable non-volatile memory controller 104 includes a memory management circuit 204, a host interface 206 and a rewritable non-volatile memory interface 208.

The memory management circuit 204 is configured for controlling the whole operation of the rewritable non-volatile memory controller 104. To be specific, the memory management circuit 204 has a plurality of control instructions, and the control instructions are executed to manage the memory module 106 according to a data writing mechanism and a memory management mechanism of the present exemplary embodiment when the rewritable non-volatile memory storage apparatus is operated. The data writing mechanism and the memory management mechanism will be described with drawings in the following.

In the present embodiment, the control instructions of the memory management circuit 204 are implemented in a firmware form. For example, the memory management circuit 204 has a micro-processor unit (not shown) and a read-only memory (not shown), and the control instructions are burned in the read-only memory. When the rewritable non-volatile memory storage apparatus is operated, the control instructions are executed by the micro-processor unit to accomplish the data writing mechanism and the memory management mechanism according to the present exemplary embodiment.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 204 are stored in a specific area (for example, the system area of the memory module exclusively used for storing system data) of the memory module 106 as program codes. Additionally, the memory management circuit 204 may have a micro-processor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). And, the read-only memory has a driver code, and when the rewritable non-volatile memory controller is enabled, the micro-processor unit executes the driver code to load the control instructions of the memory management circuit 204 stored in the memory module 106 into the random access memory of the memory management circuit 204, and then accomplish the data writing mechanism and the memory management mechanism according to the exemplary embodiment based on the control instructions. Additionally, in another exemplary embodiment, the control instructions of the memory management circuit 204 may be implemented in a hardware form.

The host interface 206 is coupled to the memory management circuit 204, and configured for receiving and identifying commands and data from the host system 1000. Namely, the commands and data from the host system 1000 are transmitted to the memory management circuit 204 through the host interface 206. In the present exemplary embodiment, the host interface 206 is a USB interface, complying with the USB 3.0 standard, corresponding to the connector 102. Nevertheless, it should be understood that the present invention is not limited thereto, and the host interface 206 may be other suitable data transmission interface.

The rewritable non-volatile memory interface 208 is coupled to the memory management circuit 204 and used for accessing the memory module 106. Namely, data to be written into the memory module 106 is converted by the rewritable non-volatile memory interface 208 into a format acceptable to the memory module 106.

In another exemplary embodiment of the present invention, the rewritable non-volatile memory controller 104 still includes a buffer memory 252. The buffer memory 252 is coupled to the memory management circuit 204 and configured to temporarily store data and commands from the host system 1000 or data from the memory module 106.

In another exemplary embodiment of the present invention, the rewritable non-volatile memory controller 104 still includes a power management circuit 254. The power management circuit 254 is coupled to the memory management circuit 204 and used for controlling the power of the rewritable non-volatile memory storage apparatus 100.

In another exemplary embodiment of the present invention, the rewritable non-volatile memory controller 104 still includes an error checking and correcting circuit 256. The error checking and correcting unit 256 is coupled to the memory management circuit 204, and configured for executing an error checking and correcting procedure to ensure data accuracy. To be specific, when the memory management circuit 204 receives a write command from the host system 1000, the error checking and correcting unit 256 generates an error checking and correcting (ECC) code for the data corresponding to the write command, and the memory management circuit 204 writes the data and the corresponding ECC code into the memory module 106. Subsequently, when the memory management circuit 204 reads the data from the memory module 106, the memory management circuit 204 simultaneously reads the corresponding ECC code, and the error checking and correcting unit 256 executes the ECC procedure for the read data based on the ECC code corresponding to the read data.

Referring to FIG. 3 again, the memory module 106 is coupled to the rewritable non-volatile memory controller 104. Herein, the memory module 106 is a multi-level cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the memory module 106 may also be a single level cell (SLC) NAND flash memory module or other rewritable non-volatile memory module.

In the present exemplary embodiment, the memory module 106 may have memory units 200-0˜200-7. In the present exemplary embodiment, the memory unit 200-0 has memory dies 210-0 and 210-1, the memory unit 200-1 has memory dies 210-2 and 210-3, the memory unit 200-2 has memory dies 210-4 and 210-5, the memory unit 200-3 has memory dies 210-6 and 210-7, the memory unit 200-4 has memory dies 210-8 and 210-9, the memory unit 200-5 has memory dies 210-10 and 210-11, the memory unit 200-6 has memory dies 210-12 and 210-13, and the memory unit 200-7 has memory dies 210-14 and 210-15.

The memory dies 210-0˜210-15 respectively have a plurality of physical blocks (not shown) for storing data. In the memory module 106, the smallest unit for erasing data is one physical block. Namely, each physical block contains the least number of memory cells that are erased together. Each physical block has several physical pages, and the smallest unit for programming data is one physical page. In other words, each physical page is the smallest unit for writing data or reading data. Each physical page usually includes a user data bit area and a redundant bit area. The user data bit area is used for storing user data, and the redundant bit area is used for storing system data (for example, the ECC code).

In the present exemplary embodiment, the rewritable non-volatile memory interface 208 of the rewritable non-volatile memory controller 104 transmits data to the memory units 200-0˜200-7 through data input/output buses 220-0˜220-7, respectively. To be specific, the rewritable non-volatile memory controller 104 transmits data to the memory dies 210-0 and 210-1 through the data input/output bus 220-0. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-2 and 210-3 through the data input/output bus 220-1. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-4 and 210-5 through the data input/output bus 220-2. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-6 and 210-7 through the data input/output bus 220-3. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-8 and 210-9 through the data input/output bus 220-4. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-10 and 210-11 through the data input/output bus 220-5. The rewritable non-volatile memory controller 104 transmits data to the memory dies 210-12 and 210-13 through the data input/output bus 220-6. And, the rewritable non-volatile memory controller 104 transmits data to the memory dies 210-14 and 210-15 through the data input/output bus 220-7.

In the present exemplary embodiment, the memory management circuit 204 groups the physical blocks of the memory dies 210-0˜210-15 into a plurality of physical units and manages the memory dies 210-0˜210-15 in a unit of each physical unit. In particular, each of the physical units is composed of several physical blocks which respectively belong to one of the memory dies. Therefore, the memory management circuit 204 may use a parallel mode and a interleave mode to increase the speed for writing data.

To be specific, because each memory unit is coupled to the rewritable non-volatile memory controller 104 by an individual data input/output bus, in the parallel mode, the memory management circuit 204 simultaneously transmits pieces of data to several memory units through several data input/output buses to increase the speed of accessing data. That is, when writing data into one physical unit, because the physical unit is composed of physical blocks belonging to different memory units, the memory management circuit 204 simultaneously transmits and writes data corresponding to the physical pages of different physical block through several data input/output buses in the parallel mode.

Moreover, because each memory unit may include two memory dies, in the interleave mode, the memory management circuit 204 alternately uses the corresponding data input/output buses to transmit data to the two memory dies in the same memory module, thereby increasing the speed of accessing data. To be specific, as described above, the procedure of writing data into a memory die may be divided into a data transfer portion and a data program portion. Herein, the interleave mode means a writing mode that data may be transmitted to one memory die during another data is programmed into another memory die when the two memory dies share the same data input/output bus to receive data.

It should be mentioned that in the present exemplary embodiment, the memory management circuit 204 determines whether the number of memory dies that are enabled at the same time should be limited within a predetermined threshold according to the power supplied by the data transmission interface 1110. To be specific, the rewritable non-volatile memory storage apparatus 100 operates with the power supplied by the data transmission interface 1110 of the host system 1000. Therefore, the number of memory dies that can be enabled at the same time is varied according to different data transmission interface in the rewritable non-volatile memory storage apparatus 100.

For example, when the data transmission interface 1110 complies with the USB 3.0 standard, the data transmission interface 1110 may supply the power having 900 milliamperes. Therefore, in the present exemplary embodiment, the memory management circuit 204 writes data without limiting the number of memory dies that can be enabled at the same time. Herein, the writing without limiting the number of memory dies that can be enabled at the same time is referred to as “a general mode”.

For example, when the data transmission interface 1110 complies with the USB 2.0 standard, the data transmission interface 1110 may only supply the power having 500 milliamperes. Therefore, the memory management circuit 204 sets the predetermined threshold as 12 for limiting that the number of memory dies that can be enabled at the same time is not larger than 12. That is, the predetermined threshold is set according to the type of the data transmission interface 1110.

For example, in an exemplary embodiment, the memory management circuit 204 may receive a detection signal from the host interface 206 to identify the type of the data transmission interface 1110 and thereby set the predetermined threshold. To be specific, when the connector 102 is coupled to the data transmission interface 1110, the host interface 202 may detect the type of the data transmission interface 1110 and the memory management circuit 204 may read the detection signal from the host interface 206. Or, in another exemplary embodiment, the memory management circuit 204 may detect the transmission speed between the host interface 206 and the data transmission interface to identify the type of the data transmission interface 1110 and thereby set the predetermined threshold. For example, the memory management circuit 204 includes a timer (not shown) and measures whether the quantity of data read by the host system 1000 from the buffer memory 252 is larger than the quantity of data read by the memory management circuit 204 from the buffer memory 252 to the host system 1000 during a period counted by the timer, thereby calculating the speed of receiving data by the host system 1000 and the speed of transmitting data by the memory module 106. And, the type of the data transmission interface can be identified by determining whether the speed of receiving data by the host system 1000 is closed to or larger than the speed of transmitting data by the memory module 106. For example, in the exemplary embodiment, the memory units of the memory module 106 transmit data through eight data input/output buses. The transmission speed of each data input/output bus is 320 megabits per second, and therefore the read speed of the memory module 106 is 2560 megabits per second. Because the speed of the USB 2.0 standard is 480 megabits per second and the speed of the USB 3.0 standard is 5000 megabits per second, the data transmission interface 1110 of the host system 1000 should complies the USB 3.0 standard if the speed of reading data by the host system 1000 is closed to or larger than 2560 megabits per second. In the present exemplary embodiment, when the speed of reading data by the host system 1000 is between 2560 megabits per second and 3060 megabits per second, it is identified that the speed of reading data by the host system 1000 is closed to 2560 megabits per second, but the invention is limited thereto.

Herein, the writing with limiting the number of memory dies that can be enabled at the same time is referred to as “a first power saving mode”.

In the present exemplary embodiment, the memory management circuit 204 may record which memory dies are at the busy status and which memory dies are at the transmission status. For example, the memory management circuit 204 identifies an ready-busy signal to determine whether a memory die is at the busy status indicating that data is programming into the memory die or an ready status indicating that no data is programming into the memory die. Additionally, the memory management circuit 204 identifies a standby-transmission signal to determine whether a memory die is at the transmission status indicating that data is transmitting into the memory die or a standby status indicating that no data is transmitting into the memory die.

Moreover, in the present exemplary embodiment, the memory management circuit 204 may establish and maintain a busy status list and a transmission status list to record information obtained from the ready-busy signals and the standby-transmission signals. That is, when a memory die starts to be at the busy status, the memory management circuit 204 records the serial number of the memory die in the busy status list, and when the memory die has finished the data program (i.e., the memory die is at the ready status), the memory management circuit 204 deletes the serial number of the memory die from the busy status list. Similarly, when a memory die starts to be at the transmission status, the memory management circuit 204 records the serial number of the memory die in the transmission status list, and when the memory die has finished the data transfer (i.e., the memory die is at the standby status), the memory management circuit 204 deletes the serial number of the memory die from the transmission status list.

FIG. 5 is a flowchart of recording the memory die that is at the transmission status according to the first exemplary embodiment of the present invention.

Referring to FIG. 5, a procedure 400 includes an adding task for the transmission status list, which is composed of steps S401, S403 and S405, and a deleting task list for the transmission status list, which is composed of steps S407, S409, S411 and S413. The adding task for the transmission status list and the deleting task list for the transmission status list are started and executed by the memory management circuit 204 at a suitable time. For example, when the first power saving mode is used, the adding task for the transmission status list and the deleting task list for the transmission status list are executed.

In the adding task for the transmission status list, first, in step S401, the memory management circuit 204 monitors the standby-transmission signal corresponding to each memory die, and in step S403, the memory management circuit 204 determines whether a memory die starts to be at the transmission status. When a memory die starts to be at the transmission status, in step S405, the memory management circuit 204 records the serial number of the memory die in the transmission status list 450.

In the deleting task list for the transmission status list, first, in step S407, the memory management circuit 204 determines whether there is any memory die being at the transmission status based on the transmission status list 450. When there is a memory die being at the transmission status, in step S409, the memory management circuit 204 monitors the standby-transmission signal corresponding to the memory die recorded in the transmission status list 450, and in step S411, the memory management circuit 204 determines whether the memory die has finished the data transfer. For example, the memory management circuit 204 uses an interrupt manner or a polling manner to obtain the standby-transmission signal corresponding to each memory die. When the memory die is at the standby status (i.e., the memory die has finished the data transfer), in step S413, the memory management circuit 204 deletes the serial number of the memory die from the transmission status list 450.

FIG. 6 is a flowchart of recording the memory die that is at the busy status according to the first exemplary embodiment of the present invention.

Referring to FIG. 6, a procedure 500 includes an adding task for the busy status list, which is composed of steps S501, S503 and S505, and a deleting task list for the busy status list, which is composed of steps S507, S509, S511 and S513. The adding task for the busy status list and the deleting task list for the busy status list are started and executed by the memory management circuit 204 at a suitable time.

In the adding task for the busy status list, first, in step S501, the memory management circuit 204 monitors the ready-busy signal corresponding to each memory die, and in step S503, the memory management circuit 204 determines whether a memory die starts to be at the busy status. When a memory die starts to be at the busy status, in step S505, the memory management circuit 204 records the serial number of the memory die in the busy status list 460.

In the deleting task list for the busy status list, first, in step S507, the memory management circuit 204 determines whether there is any memory die being at the busy status based on the busy status list 460. When there is a memory die being at the busy status, in step S509, the memory management circuit 204 monitors the ready-busy signal corresponding to the memory die recorded in the busy status list 460, and in step S511, the memory management circuit 204 determines whether any one memory die in the busy status list 460 has finished the data program and is at the ready status. For example, the memory management circuit 204 uses an interrupt manner or a polling manner to obtain the ready-busy signal corresponding to each memory die. When any memory die in the busy status list 460 is at the ready status (i.e., the memory die has finished the data program), in step S513, the memory management circuit 204 deletes the serial number of the memory die from the busy status list 460.

In the first power saving mode, whenever the rewritable non-volatile memory controller 104 is about to write data written by the host system 1000 into a memory die of the memory module 106, the memory management circuit 204 calculates the number of memory dies that currently are enabled (i.e., at the busy status and the transmission status) based on the busy status list 460 and the transmission status list 450. In particular, the memory management circuit 204 writes the data into the corresponding memory die only when the number of memory dies that currently are enabled in the memory module 106 is smaller than the predetermined threshold. On the contrary, when the number of memory dies that currently are enabled in the memory module 106 is not smaller than the predetermined threshold, the memory management circuit 204 waits and continuously monitors the ready-busy signals and the standby-transmission signals corresponding the memory dies that are enabled (as the procedures shown in FIG. 5 and FIG. 6).

FIG. 7 is a flowchart of writing data in the first power saving mode according to the first exemplary embodiment of the present invention.

Referring to FIG. 7, when the rewritable non-volatile memory controller 104 is about to write data written by the host system 1000 into a memory die of the memory module 106, in step S601, the memory management circuit 204 calculates the number of memory dies that currently are at the transmission status based on the transmission status list 450, and in step S603, the memory management circuit 204 calculates the number of memory dies that currently are at the busy status based on the busy status list 460.

Then, in step S605, the memory management circuit 204 sums the number of memory dies that currently are at the transmission status and the number of memory dies that currently are at the busy status to obtain the number of memory dies that currently are enabled.

After that, in step S607, memory management circuit 204 determines whether the number of memory dies that currently are enabled in the memory module 106 is smaller than the predetermined threshold. If the number of memory dies that currently are enabled in the memory module 106 is smaller than the predetermined threshold, in step S609, the memory management circuit 204 writes the data into the corresponding memory die. If the number of memory dies that currently are enabled in the memory module 106 is not smaller than the predetermined threshold, then step S601 is executed.

In should be noted that in the first power saving mode, the memory management circuit 204 determines whether the data should be written immediately into the memory die based on the number memory dies that currently are enabled in the memory module 106. However, in another exemplary embodiment of the present invention, the memory management circuit 204 may group the physical units 200-0˜200-7 into several memory unit groups and only writes data into the memory units of one of the memory unit groups at the same time. Herein, the number of memory dies in the same memory unit group is set based on the hardware design of the memory module 106 and the lowest power supplied by the data transmission interface.

For example, the memory management circuit 204 may group the memory units 200-0˜200-1 into a first memory unit group, group the memory units 200-2˜200-3 into a second memory unit group, group the memory units 200-4˜200-5 into a third memory unit group and group the memory units 200-6˜200-7 into a forth memory unit group. When data is about to be written into the memory units 200-0˜200-7, the memory management circuit 204 may transmit corresponding data to the memory units 200-0˜200-1. Then, after the memory units 200-0˜200-1 have finished the data program, the memory management circuit 204 may transmit corresponding data to the memory units 200-2˜200-3. After the memory units 200-2˜200-3 have finished the data program, the memory management circuit 204 may transmit corresponding data to the memory units 200-4˜200-5. Finally, after the memory units 200-4˜200-5 have finished the data program, the memory management circuit 204 may transmit corresponding data to the memory units 200-6˜200-7. Accordingly, it can prevent the memory units 200-0˜200-7 from being enabled at the same time.

Second Exemplary Embodiment

A rewritable non-volatile memory storage apparatus and a host system of the second exemplary embodiment substantially is the same as the rewritable non-volatile memory storage apparatus and the host system of the first exemplary embodiment. Herein, only the difference of the second exemplary embodiment will be described with FIG. 2A, FIG. 3 and FIG. 4.

Similar to the first exemplary embodiment, the control instructions of the memory management circuit 204 are executed by the micro-processor unit to accomplish the data writing mechanism and the memory management mechanism according to the second exemplary embodiment. The difference between the first exemplary embodiment and the second exemplary embodiment is that the memory management circuit 204 determines whether data can be written immediately according to the number of memory dies that currently are enabled in the first power saving mode in the first exemplary embodiment. However, in the second exemplary embodiment, the memory management circuit 204 closes the interleave mode to limit the number of memory dies that are enabled at the same time in the first power saving mode.

To be specific, the memory management circuit 204 receives a detection signal from the host interface 206 to identify the type of the data transmission interface 1110. In particular, when the data transmission interface 1110 belongs a kind of a transmission interface that only can supply lower power (e.g., USB 2.0), the rewritable non-volatile memory controller does not use the interleave mode to write data into the memory module 106, thereby avoiding that the power consumption of the rewritable non-volatile memory storage apparatus 100 exceeds the power supplied by the data transmission interface 1110. For example, in the present exemplary embodiment, when the memory management circuit 204 only uses the parallel mode to write data, the number of memory dies that are enabled at the same time is limited within 8.

FIG. 8 is a flowchart of writing data according to the second exemplary embodiment of the present invention.

Referring to FIG. 8, when the rewritable non-volatile memory controller 104 is about to write data written by the host system 1000 into a memory die of the memory module 106, in step S701, the memory management circuit 204 receives a detection signal from the host interface 206 to identify the type of the data transmission interface 1110.

After that, in step S703, the memory management circuit 204 determines whether the data transmission interface 1110 complies with a first interface standard that can supply enough power (e.g., USB 3.0).

If the data transmission interface 1110 complies with the first interface that can supply enough power, in step S705, the memory management circuit 204 uses the interleave mode to write the data into the memory module 106.

If the data transmission interface 1110 does not comply with the first interface standard that can supply enough power (i.e., the data transmission interface 1110 complies with a second interface standard that can not supply enough power (e.g., USB 2.0)), in step S707, memory management circuit 204 closes the interleave mode and does not use the interleave mode to write the data into the memory module 106.

Third Embodiment

FIG. 9 is a schematic block diagram of a rewritable non-volatile memory controller according to a third exemplary embodiment of the present invention.

Referring to FIG. 9, the rewritable non-volatile memory storage apparatus 800 includes the connector 102, a rewritable non-volatile memory controller 804, and the memory module 106.

The rewritable non-volatile memory controller 804 executes a plurality of logic gates or control instructions implemented in a hardware form or a firmware form and performs various data operations such as data writing, reading, and erasing in the memory module 106 according to commands from the host system 1000.

The rewritable non-volatile memory controller 804 includes a memory management circuit 814, the host interface 206, the rewritable non-volatile memory interface 208, the buffer memory 252, the ECC circuit 256 and a power management circuit 854.

The memory management circuit 814 is configured for controlling the whole operation of the rewritable non-volatile memory controller 804. To be specific, the memory management circuit 814 has a plurality of control instructions, and the control instructions are executed to write, read or erase data in the memory module 106 when the rewritable non-volatile memory storage apparatus 800 is operated.

In the third exemplary embodiment, similar to the memory management circuit 204 of the first exemplary embodiment, the memory management circuit 814 may be implemented in a firmware form or a hardware form or implemented as program codes.

The power management circuit 854 is coupled to the memory management circuit 814 and used for controlling the power of the rewritable non-volatile memory storage apparatus 800. The power management circuit 854 includes a phase locked loop (PLL) 862 for generating an operation frequency for the rewritable non-volatile memory controller 804 and the memory module 106. That is, the rewritable non-volatile memory controller 804 and the memory module 106 operate with the operation frequency generated by the PLL 862.

In the third exemplary embodiment, the power management circuit 854 may identify the standard of the data transmission interface 1110 and PLL 862 generates the corresponding operation frequency based on the standard of the data transmission interface 1110. For example, the power management circuit 854 may receive a detection signal from the host interface 206 to identify the type of the data transmission interface 1110.

To be specific, the memory management circuit 814 may use the above-mentioned parallel mode and interleave mode to access the memory module 106, thereby increasing the speed of accessing data. However, the power supplied by the data transmission interface 1110 may be not enough, such that the data program may fail. For examples, when the parallel mode and the interleave mode both are used, all the memory dies of the memory module 106 may be enabled at the same time. However, if the power supplied by the data transmission interface 1110 is not enough to enable all the memory dies of the memory module 106, some errors may occur during the memory management circuit 814 writes data into the memory module 106.

In the third exemplary embodiment, when the data transmission interface 1110 can not supply enough power, the PLL 862 may generate lower operation frequency, such that the rewritable non-volatile memory controller 804 and the memory module 106 can operate stably. To be specific, because currents represent an amount of charges that pass during the unit time (i.e., I=Q/T), the currents are proportional to the operation frequency. And, the currents are proportional to the power, and therefore the operation frequency is proportional to the power. Accordingly, using lower operation frequency can save more power.

For example, when the data transmission interface 1110 complies with the USB 3.0 standard, the data transmission interface 1110 may supply the power having 900 milliamperes. Therefore, in the third exemplary embodiment, the PLL 862 of the power management circuit 854 generates a first operation frequency (e.g., 125 MHz) for the rewritable non-volatile memory controller 804 and the memory module 106.

For example, when the data transmission interface 1110 complies with the USB 2.0 standard, the data transmission interface 1110 may only supply the power having 500 milliamperes. Therefore, in the third exemplary embodiment, the PLL 862 of the power management circuit 854 generates a second operation frequency (e.g., 60 MHz) for the rewritable non-volatile memory controller 804 and the memory module 106. Herein, a mode that the rewritable non-volatile memory controller 804 and the memory module 106 operate with the second operation frequency is also referred to as “a second power saving mode”.

Accordingly, the rewritable non-volatile memory controller 804 and the memory module 106 can operate stably, no matter the data transmission interface 1110 complies with the USB 2.0 standard or the USB 3.0 standard.

FIG. 10 is a flowchart of writing data according to the third exemplary embodiment of the present invention.

Referring to FIG. 10, when the rewritable non-volatile memory storage apparatus 800 is coupled to the host system 1000, in step S901, the power management circuit 854 of the rewritable non-volatile memory controller 804 receives a detection signal from the host interface 204 to identify the type of the data transmission interface 1110.

After that, in step S903, the power management circuit 854 determines whether the data transmission interface 1110 complies with a first interface standard that can supply enough power (e.g., USB 3.0).

If the data transmission interface 1110 complies with the first interface that can supply enough power, in step S905, the PLL 862 generates the first operation frequency for the memory management circuit 814 and the memory module 106. Then, in step S907, the memory management circuit 814 writes the data written by the host system 1000 into the memory module 106 with the first operation frequency.

If the data transmission interface 1110 does not comply with the first interface that can supply enough power (i.e., the data transmission interface 1110 complies with the second interface that can not supply enough power (e.g., USB 2.0)), in step S909, the PLL 862 generates the second operation frequency for the memory management circuit 814 and the memory module 106. Then, in step S911, the memory management circuit 814 writes the data written by the host system 1000 into the memory module 106 with the second operation frequency.

In summary, the data writing method according to the exemplary embodiments of the present invention uses the general mode or the power saving mode to write data based on the type of the data transmission interface of the host system. Accordingly, the number of memory dies that are enabled at the same time can be limited when the data transmission interface can not supply enough power, and thereby the above-mentioned stability issue due to the insufficient power can be prevented when the parallel mode and the interleave mode may be used for writing data. The previously described exemplary embodiments of the present invention have the advantages aforementioned, wherein the advantages aforementioned not required in all versions of the invention.

Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions. 

1. A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus, wherein a host interface of the rewritable non-volatile memory storage apparatus is adapted for coupling to a data transmission interface of the host system, the data writing method comprising: determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information after the data transmission interface couples to the host interface; using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard, wherein the number of memory dies that are enabled at the same time among the memory dies is not larger than a first amount and the memory dies operate with a first operation frequency in the general mode; and using a first power saving mode or a second power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard, wherein, the number of the memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode, and the second amount is smaller than the first amount, wherein the memory dies operate with a second operation frequency in the second power saving mode, and the second operation frequency is smaller than the first operation frequency.
 2. The data writing method according to claim 1 further comprising: receiving a detection signal to obtain the information or measuring a transmission speed of the data transmission interface to obtain the information.
 3. The data writing method according to claim 1 further comprising: wherein the step of using the general mode to write the data into the memory dies comprises: writing the data into the memory dies with using an interleave mode, wherein the step of using the first power saving mode to write the data into the memory dies comprises: writing the data into the memory dies without using the interleave mode.
 4. The data writing method according to claim 1, wherein the first interface standard is a universal serial bus (USB) 3.0 standard, and the second interface standard is a universal serial bus (USB) 2.0 standard.
 5. The data writing method according to claim 1, wherein the step of using the first power saving mode to write the data into the memory dies comprises: recording the number of memory dies that are at a busy status among the memory dies; recording the number of memory dies that are at a transmission status among the memory dies; determining whether a sum of the number of memory dies that are at the busy status and the number of memory dies that are at the transmission status is smaller than a predetermined threshold; and writing the data into one of the memory dies when the sum is smaller than the predetermined threshold, wherein the memory die written with the data is neither at the busy status nor the transmission status.
 6. The data writing method according to claim 5, wherein the step of recording the number of memory dies that are at the busy status among the memory dies comprises: monitoring a ready-busy signal corresponding to each of the memory dies; adding a first memory die among the memory dies in a busy status list when the ready-busy signal corresponding to the first memory die becomes the busy status from an ready status; deleting the first memory die from the busy status list when the ready-busy signal corresponding to the first memory die becomes the ready status from the busy status; and calculating the number of memory dies that are at the busy status among the memory dies according to the busy status list, wherein the step of recording the number of memory dies that are at the transmission status among the memory dies comprises: monitoring a standby-transmission signal corresponding to each of the memory dies; adding a second memory die among the memory dies in a transmission status list when the standby-transmission signal corresponding to the second memory die becomes the transmission status from a standby status; deleting the second memory die from the transmission status list when the ready-busy signal corresponding to the second memory die becomes the standby status from the transmission status; and calculating the number of memory dies that are at the transmission status among the memory dies according to the transmission status list.
 7. A rewritable non-volatile memory controller for writing data from a host system into a plurality of memory dies, the rewritable non-volatile memory controller comprising: a host interface, configured to couple to a data transmission interface of the host system; a rewritable non-volatile memory interface, configured to couple to the memory dies; and a memory management circuit, coupled to the host interface and the rewritable non-volatile memory interface, wherein the memory management circuit is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information, wherein the memory management circuit uses a general mode to write the data into the memory dies when the data transmission interface complies with the first interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a first amount in the general mode, wherein the memory management circuit uses a first power saving mode to write the data into the memory dies when the data transmission interface complies with the second interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode and the second amount is smaller than the first amount.
 8. The rewritable non-volatile memory controller according to claim 7, wherein the memory management circuit is further configured to receive a detection signal to obtain the information or measure a transmission speed of the data transmission interface to obtain the information.
 9. The rewritable non-volatile memory controller according to claim 7, wherein the memory management circuit writes the data into the memory dies with using an interleave mode in the general mode, wherein the memory management circuit writes the data into the memory dies without using the interleave mode in the first power saving mode.
 10. The rewritable non-volatile memory controller according to claim 7, wherein in the first power saving mode, the memory management circuit records the number of memory dies that are at a busy status among the memory dies, records the number of memory dies that are at a transmission status among the memory dies, determines whether a sum of the number of memory dies that are at the busy status and the number of memory dies that are at the transmission status is smaller than a predetermined threshold and writes the data into one of the memory dies when the sum is smaller than the predetermined threshold, wherein the memory die written with the data is neither at the busy status nor the transmission status.
 11. The rewritable non-volatile memory controller according to claim 10, wherein the memory management circuit is further configured to monitor a ready-busy signal corresponding to each of the memory dies, wherein the memory management circuit adds a first memory die among the memory dies in a busy status list when the ready-busy signal corresponding to the first memory die becomes the busy status from an ready status, wherein the memory management circuit deletes the first memory die from the busy status list when the ready-busy signal corresponding to the first memory die becomes the ready status from the busy status, wherein the memory management circuit calculates the number of memory dies that are at the busy status among the memory dies according to the busy status list and monitors a standby-transmission signal corresponding to each of the memory dies, wherein the memory management circuit adds a second memory die among the memory dies in a transmission status list when the standby-transmission signal corresponding to the second memory die becomes the transmission status from a standby status, wherein the memory management circuit deletes the second the memory die from the transmission status list when the ready-busy signal corresponding to the second memory die becomes the standby status from the transmission status, wherein the memory management circuit calculates the number of memory dies that are at the transmission status among the memory dies according to the transmission status list.
 12. A rewritable non-volatile memory storage system, comprising: a connector, configured to couple to a data transmission interface of a host system; a memory module, having a plurality of memory dies; and a rewritable non-volatile memory controller, coupled to the memory module and the connector, and configured to determine whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information. wherein the rewritable non-volatile memory controller uses a general mode to write the data into the memory dies when the data transmission interface complies with the first interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a first amount in the general mode, wherein the rewritable non-volatile memory controller uses a first power saving mode to write the data into the memory dies when the data transmission interface complies with the second interface standard, wherein the number of memory dies that are enabled at the same time is not larger than a second amount in the first power saving mode, wherein the second amount is smaller than the first amount.
 13. The rewritable non-volatile memory storage system according to claim 12, wherein the rewritable non-volatile memory controller is further configured to receive a detection signal to obtain the information or measure a transmission speed of the data transmission interface to obtain the information.
 14. The rewritable non-volatile memory storage system according to claim 12, wherein the rewritable non-volatile memory controller writes the data into the memory dies with using an interleave mode in the general mode, wherein the rewritable non-volatile memory controller writes the data into the memory dies without using an interleave mode in the first power saving mode.
 15. A rewritable non-volatile memory controller for writing data from a host system into a plurality of memory dies, the rewritable non-volatile memory controller comprising: a host interface, configured to couple to a data transmission interface of the host system; a rewritable non-volatile memory interface, configured to couple to the memory dies; a power management circuit, having a phase locked loop (PLL); and a memory management circuit, coupled to the rewritable non-volatile memory interface and the power management circuit, wherein the power management circuit is configured for determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information; wherein when the data transmission interface of the host system complies with the first interface standard, the PLL generates a first operation frequency and provides the first operation frequency for the memory management circuit and the memory dies and the memory management circuit writes the data into the memory dies with the first operation frequency, wherein when the data transmission interface of the host system complies with the second interface standard, the PLL generates a second operation frequency and provides the second operation frequency for the memory management circuit and the memory dies and the memory management circuit writes the data into the memory dies with the second operation frequency.
 16. The rewritable non-volatile memory controller according to claim 15, wherein the power management circuit receives a detection signal from the host interface to obtain the information.
 17. The rewritable non-volatile memory controller according to claim 15, wherein the first interface standard is a universal serial bus (USB) 3.0 standard, and the second interface standard is a universal serial bus (USB) 2.0 standard.
 18. A rewritable non-volatile memory storage system, comprising: a connector, configured to couple to a host system; a memory module, having a plurality of memory dies; and a rewritable non-volatile memory controller, coupled to the memory module and the connector, wherein the rewritable non-volatile memory controller is configured to determine whether the data transmission interface of the host system complies with a first interface standard or a second interface standard according to information, wherein the rewritable non-volatile memory controller generates a first operation frequency, provides the first operation frequency for the memory dies and writes the data into the memory dies with the first operation frequency when the data transmission interface of the host system complies with the first interface standard, wherein the rewritable non-volatile memory controller generates a second operation frequency, provides the second operation frequency for the memory dies and writes the data into the memory dies with the second operation frequency when the data transmission interface of the host system complies with the second interface standard.
 19. The rewritable non-volatile memory storage system according to claim 18, wherein the rewritable non-volatile memory controller receives a detection signal from the data transmission interface to obtain the information.
 20. The rewritable non-volatile memory storage system according to claim 18, wherein the first interface standard is a universal serial bus (USB) 3.0 standard, and the second interface standard is a universal serial bus (USB) 2.0 standard. 